In data processing systems the need arises to transfer data across the system boundaries. For example, transfers between a slower I/O device and the processor system bus often involve re-synchronizing the I/O data with the system clock prior to storage in memory. It is common in the art for data from the I/O device to be accompanied by a strobe signal for each new data word. This strobe signal can occur every few cycles of the system clock signal, and is desirably converted into a signal which changes state coincident with the system clock signal. Synchronizing circuits have been developed to accommodate this need.
U.S. Pat. No. 4,745,302 to Hanawa et al. discloses a synchronizer in which four level-sensitive latches are used to synchronize an external signal to the internal clock in one-fourth of a clock cycle. A primary clock signal is divided into two secondary clock signals and the four latches are clocked by different ones of the secondary and complemented secondary clock signals. Since it is clocked, this circuit may miss a strobe which occurs between clock pulses.
U.S. Pat. No. 4,615,017 to Finlay et al. relates to a memory interface circuit that couples a memory to either a synchronous bus or an asynchronous bus. In this system, an asynchronous memory access request signal is latched using the local memory clock signal. A data transfer acknowledge signal is derived from the synchronized memory access request signal. As with the circuit disclosed in Hanawa, proper synchronization only occurs when the data input signals to the latch are stable prior to the arrival of the clock signal. A data strobe pulse having a short duration relative to the period of the system clock signal could be missed.
FIGS. 1a and 1b show synchronizing circuits suitable for synchronizing short input pulses. Each circuit uses a series of flip flops to acquire an asynchronous input strobe signal and produce an output pulse that is synchronized to the system clock signal. The initial flip flop 22 in the series uses the positive-going edge of the asynchronous signal STROBE to propagate a logic high level from a source of logic high 20 to its Q output terminal. After some delay, the flip flop 22 is cleared to a logic low level through a pulse signal applied to an asynchronous reset terminal, to await the arrival of the next asynchronous strobe pulse.
A low to high logic transition of the signal provided by output terminal Q of the flip flop 22 indicates that an asynchronous input strobe has been received by the circuit. A disadvantage of using the low to high state transition in this manner is that the first stage flip flop must be reset between pulses.
In FIG. 1a, the reset signal is obtained from the reclocked version of the input strobe. When the asynchronous input strobe signal is asserted, the flip flop 22 changes the state of its output from low to high. The input terminal D of flip flop 24 is coupled to the output terminal of flip flop 22. A data bit present on the output terminal of flip flop 22 is captured by the flip flop 24 responsive to the system clock signal. This data bit then appears at the output terminal Q of the second flip flop 24.
Since the input signal to the second flip flop is asynchronous to the system clock signal, the second flip flop's output signal may be metastable. That is, if the required input signal setup time is not met, the output signal may oscillate between logic low and logic high. It settles eventually to a recognized state, but to compensate for the possible metastability, a third flip flop stage 26 must be used to ensure that a stable synchronization pulse is produced.
The input terminal D of the flip flop 28 is coupled to data output terminal Q of the flip flop 26. Responsive to the system clock signal, the flip flop 28 captures data applied to its D input terminal and places it on the Q output terminal. An output pulse signal SYNC is formed by applying the data output signals from flip flop 26 and flip flop 28 to an exclusive-OR gate 30. In the circuit implementation shown in FIG. 1a, this output signal SYNC is then fed back through an inverter 32 to the asynchronous reset input terminal on the flip flop 22. It is in response to this signal that the flip flop 22 resets its output signal to a low logic level, to prepare for the next input strobe pulse. A problem with this implementation is that the frequency of the clock signal must be high relative to the period between strobes. If the frequency of the system clock is too low, then the first flip flop may be in the process of resetting itself when the next asynchronous input strobe is received.
In FIG. 1b, the output signal Q of the first flip flop 42 is fed back through an adjustable delay line 50. The delayed signal is then applied to the asynchronous reset input terminal of the flip flop 42. The adjustable delay line is programmable to provide one of several possible delay times to the signal provided to its input terminal. This has the disadvantage of requiring an expensive extra component and its required board space. In addition, two extra input pins to the synchronizer integrated circuit may be required for interconnection to the adjustable delay line component.
The output stage of each of the two prior art synchronizing circuits includes an exclusive-OR gate. As set forth above, the input signals provided to this gate are the output signals from the third and fourth flip flops in each circuit, respectively. The SYNC output signal thus produced by the exclusive-OR gate is an active high pulse, one clock cycle in duration.
However, the propagation delay through the exclusive-OR gate, on the order of several nanoseconds (ns), imposes a penalty on system performance. The resulting SYNC output signal is not available until later in the clock cycle, and its worst case delay time is increased. Further, this implementation is capable of producing an output pulse only once every three system clock cycles.